1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a multi-input semiconductor logic device having a logic function such as an AND, OR, NOT, NAND, and NOR, in which an output signal has an approximately constant switching speed independent of the logic condition or state of input signals.
2. Description of the Prior Art
In general, a multi-input logic circuit with the Complementary Metal-Oxide-Semiconductor (CMOS) configuration is expressed as the combination of basic logic subcircuits such as AND, OR, and NOT.
In the mask design for these basic logic subcircuits to be used for a multi-input semiconductor logic device, it is important that the "artwork" (i.e., mask pattern) is made to minimize the parasitic capacitance of the semiconductor logic device. This is because the minimized parasitic capacitance contributes to high-speed operation of the logic device and makes it possible to decrease the electric power dissipation thereof.
Additionally, it is important that the artwork is made to minimize the parasitic resistance of the logic device.
To realize the minimization of the parasitic capacitance and parasitic resistance, conventionally, various improvements have been provided. An example of the conventional improved artworks or layout and a corresponding circuit configuration are shown in FIGS. 2 and 1, respectively, which was disclosed in the Japanese Non-Examined Patent Publication No. 56-125854 published in 1981. This conventional artwork has been practically used.
As shown in FIG. 1, the conventional two-input MOS NAND circuit has a first pair of n-channel driver MOS Field-Effect Transistors (MOSFETs) TR121 and TR122, a second pair of n-channel driver MOSFETs TR131 and TR132, and an n-channel load MOSFET TR101.
A drain and a gate of the load MOSFET TR101 are electrically connected to a power supply (riot shown) supplying a constant voltage V.sub.DD. A source of the load MOSFET TR101 is electrically connected to an output terminal OUT and coupled drains of the driver MOSFETs TR121 and TR122.
Gates of the driver MOSFETs TR121 and TR122 are coupled together to be electrically connected to a first input terminal IN.sub.A. Gates of the driver MOSFETs TR131 and TR132 are coupled together to be electrically connected to a second input terminal IN.sub.B. Sources of the driver MOSFETs TR121 and TR122 are electrically connected to drains of the driver MOSFETs TR131 and TR132, respectively. In other words, the driver MOSFETs TR121 and TR131 are connected in series, and the driver MOSFETs TR122 and TR132 are connected in series. Sources of the driver MOSFETs TR131 and TR132 are electrically connected to the ground.
The artwork or layout pattern of the conventional two-input NAND circuit in FIG. 1 is shown in FIG. 2. Only the artwork of the area S including the four driver MOSFETs TR121, TR122, TR131, and TR132 is shown in FIG. 2 for the sake of simplification.
In FIG. 2, the reference numerals 111 and 112 denote a p-type semiconductor substrate and a rectangular active area, respectively. The active area 112 is formed in the substrate 111. Five n-type source/drain regions 101, 102, 103, 104, and 105 are formed to be separated and to be electrically isolated from one another in the active area 112. The source/drain regions 101, 102, 103, 104, and 105 are arranged along the longitudinal axis of the active area 112. The n-type source/drain regions 101, 102, 103, 104, and 105 each have a rectangular shape.
The source/drain region 101 is located at the middle of the active area 112. The source/drain regions 102 and 104 are located at each side of the source/drain region 101. The source/drain regions 103 and 105 are located at each side of the source/drain region 101 to be adjacent to the source/drain regions 102 and 104, respectively.
The source/drain region 101 serves as the drains (or, common drain) of the MOSFETs TR121 and TR122. The source/drain region 102 serves as the source of the MOSFET TR121 and the drain of the MOSFET TR131. The source/drain region 103 serves as the source of the MOSFET TR131. The source/drain region 104 serves as the source of the MOSFET TR122 and the drain of the MOSFET TR132. The source/drain region 105 serves as the source of the MOSFET TR132.
An electrically-conductive layer 106, which has a U-shaped pattern, is formed to be overlapped with the active area 112 at its two arms. An overlapped part 106a of the layer 106 is located between the source/drain regions 101 and 102. Another overlapped part 106b of the layer 106 is located between the source/drain regions 101 and 104. A connection part 106c of the layer 106 is located outside the active area 112 on the left-hand side in FIG. 2. The overlapped parts 106a and 106b serve as gate electrodes of the MOSFETs TR121 and 122, respectively.
An electrically-conductive layer 107, which has a U-shaped pattern, is formed to be overlapped with the active area 112 at its two arms. An overlapped part 107a of the layer 107 is located between the source/drain regions 102 and 103. Another overlapped part 107b of the layer 107 is located between the source/drain regions 104 and 105. A connection part 107c of the layer 107 is located outside the active area 112 on the right-hand side in FIG. 2. The overlapped parts 107a and 107b serve as gate electrodes of the MOSFETs TR131 and 132, respectively.
An electrically-conductive contact 110 is formed on the source/drain region 101 to be contacted therewith. The source/drain region 101, which serves as the drain regions of the MOSFETs TR121 and TR122, is electrically connected to the output terminal OUT through the contact 110.
An electrically-conductive contact 108 is formed on the source/drain region 103 to be contacted therewith. The source/drain region 103, which serves as the source region of the MOSFET TR131, is electrically connected to the ground through the contact 108.
An electrically-conductive contact 109 is formed on the source/drain region 105 to be contacted therewith. The source/drain region 105, which serves as the source region of the MOSFET TR132, is electrically connected to the ground through the contact 109.
As described above, with the conventional artwork shown in FIG. 2, the combination of the two MOSFETs TR121 and TR122 or that of the two MOSFETs TR131 and TR132 is equivalent to a single MOSFET having a channel (or, gate electrode) width twice as large as that of the MOSFET TR121 or TR122. Therefore, the combination of the two MOSFETs TR121 and TR122 or TR131 and TR132 is less in both parasitic capacitance and parasitic resistance than the equivalent single MOSFET.
The conventional artwork shown in FIG. 2, however, has a problem that the switching speed of the output signal varies dependent upon the prior logic state of the two input signals.
Specifically, it is supposed that a first digital input signal V.sub.INA to be applied to the first input terminal IN.sub.A is in the high level or the 1 state, and a second digital input signal V.sub.INB to be applied to the second input terminal IN.sub.B is in the low level or the 0 state. This logic condition or state is expressed as (1,0) in this specification.
When the first and second input signals V.sub.INA and V.sub.INB are turned from the state (1,0) to the state (1,1), an output signal V.sub.OUT to be derived from the output terminal OUT is turned from the 1 state to the 0 state. When the first and second input signals V.sub.INA and V.sub.INB are turned from the state (0,1) to the state (1,1), the output signal V.sub.OUT is turned from the 1 state to the 0 state, which is the same as that of the signal change from the state (1,0) to the state (1,1). However, the switching or turning speed of the output signal V.sub.OUT in the former case of (1,0) to (1,1) is slower than that in the latter case of (0,1) to (1,1). The reason is as follows.
In the former case of (1,0) to (1,1), the MOSFETs TR121 and TR122 are ON (i.e., conductive) while the MOSFETs TR131 and TR132 are OFF in the state (1,0). The load MOSFET TR101 is always ON. Therefore, the drains of the MOSFETs TR131 and TR132 are in a voltage level of V.sub.DD. This means that electric charges are stored in parasitic capacitors existing in the neighborhood of the source/drain regions 102 and 104 and that electric charges are stored in parasitic capacitors existing in the neighborhood of the source/drain region 101. As a result, the stored charges in the parasitic capacitors relating to the source/drain regions 102 and 104 need to be discharged at the switching time from the (1,0) to (1,1), thereby increasing the switching time of the output signal V.sub.OUT.
On the other hand, in the latter case of (0,1) to (1,1), the MOSFETs TR121 and TR122 are OFF while the MOSFETs TR131 and TR132 are ON in the state (0,1). Therefore, the drains of the MOSFETs TR131 and TR132 are in a voltage level of 0, i.e., in the ground level. This means that electric charges are stored in the parasitic capacitors existing in the neighborhood of the source/drain region 101, and that no electric charges are stored in the parasitic capacitors existing in the neighborhood of the source/drain regions 102 and 104. As a result, the stored charges in the parasitic capacitors relating to the source/drain region 101 need to be discharged at the switching time from the (0,1) to (1,1), thereby increasing the switching time of the output signal V.sub.OUT.
Because the stored charges in the parasitic capacitors relating to the source/drain regions 102 and 104 are greater than those in the parasitic capacitors relating to the source/drain region 101, the switching time of the output signal V.sub.OUT in the case of (1,0) to (1,1) is longer than that in the case of (0,1) to (1,1). In other words, the switching or turning of the output signal V.sub.OUT in the case of (1,0) to (1,1) occurs later than that in the case of (0,1) to (1,1).
The same phenomenon occurs in the case where the output signal V.sub.OUT is turned from the 0 state to the 1 state.
For example, the parasitic capacitors relating to the source/drain regions 102 and 104 are typically formed by the combination of (a) the source/drain regions 102 and 104 and the corresponding gate electrodes 106a and 106b, (b) the source/drain regions 102 and 104 and the substrate, and (c) the source/drain regions 102 and 104 and wiring or interconnection layers (not shown in FIGS. 1 and 2).
The above switching speed or time difference of the output signal V.sub.OUT varies dependent upon the size of the MOSFETs TR121, TR122, TR131, and TR132.
The above switching speed difference requires a comparatively large margin in design of an operation timing or clock signal of the semiconductor logic device including the conventional two-input MOS NAND circuit. This large margin will lower the operation speed of the device.